RISC-V from Software to Silicon: Programming, Linux, FPGA, and AI Applications Training Course

RISC-V Architectural Basics and Ecosystem Insights

RISC-V ISA Landscape and Market Adoption

• The philosophy of open ISAs and the standardization environment led by RISC-V International
• Conceptualizing RISC-V: Load-Store architecture, register files, and byte ordering
• Benchmarking against ARM, x86, and POWER: evaluating trade-offs for heterogeneous computing designs
• Assessing ecosystem maturity: contributions from SiFive, T-Head, Western Digital, and the expanding open-source silicon community
• Standardized interfaces: RISC-V Privileged ISA and the Machine Software Abstraction Layer (MSBL)

Memory Models and ABI Adherence

• Unprivileged Architecture specifications: CSR maps, exception handling, and memory hierarchies
• RV32I / RV64I instruction sets and ABI compliance for cross-platform binary compatibility
• Memory ordering rules and barrier instructions for multi-processor systems

RISC-V Assembly Coding and Compiler Toolchains

Low-Level Instruction Coding

• Foundational integer instructions (I), Multiply/Divide (M), and Atomic operations (A) extensions
• Programming strategies mindful of bitness for 32-bit and 64-bit RISC-V targets
• Calling conventions and stack frame management for embedded and real-time software environments

Compiler Toolchain Expertise

• LLVM-based toolchain: Clang, LLVM, and Binutils for RISC-V cross-compilation
• Configuring linker scripts, sections, and memory layout for bare-metal and RTOS contexts
• Utilizing compiler intrinsics, optimization levels, and profiling-driven code refinement
• Workflows for open-source toolchain development: creating, testing, and packaging custom GCC/Clang toolchains

Embedded System Development and Real-Time Operating Systems

Bare-Metal and RTOS Programming

• Rust systems programming for RISC-V: zero-cost abstractions, unsafe memory management, and bare-metal development
• No-Std environments: custom linkers, device driver creation, and memory-mapped I/O
• Developing Zephyr RTOS and Buildroot BSPs for RISC-V targets
• Peripheral interfacing: programming GPIO, I2C, SPI, UART, and DMA controllers

Power and Performance Optimization

• Clock gating, power domain management, and low-power mode optimization
• Cycle-accurate performance analysis using simulation profilers and hardware performance counters
• Tuning real-time interrupt latency for safety-critical applications

Linux Kernel and Bootloader Development for RISC-V

Boot Firmware and Bootloader Ecosystem

• OpenSBI (implementation of the SBI specification): developing bootloader firmware
• UEFI/EDK II on RISC-V: building modern firmware boot stacks
• Porting Coreboot and U-Boot for RISC-V single-board computers

Linux Kernel Integration

• Contributions to the RISC-V mainline kernel: device tree overlays, CPU topology, and interrupt controller (AIA) driver development
• Vendor BSP development and kernel configuration for custom SoC platforms
• Support for file systems, networking stacks, and containerization (Docker, Kubernetes) on RISC-V hosts

RISC-V SoC Design and FPGA Prototyping

Multicore SoC Architecture and Integration

• Network-on-Chip (NoC) design methodologies for RISC-V multi-core processors
• Axi4/CHI cache coherence and inter-processor communication protocols
• Integrating open-source IP: OpenCores, ChIPS Framework, and vendor RTL components
• Bus matrix design and memory controller integration (DDR, SRAM, eMMC, PCIe)

FPGA-Based Processor Prototyping

• FPGA synthesis and implementation of RISC-V cores (e.g., BOOM, VexRiscv, PULP)
• SystemVerilog Assertions (SVA) and UVM-based functional verification methodologies
• Formal verification tools and property-based testing for RISC-V core validation

RISC-V Vector Extensions and Domain-Specific Acceleration

Deep Dive into RVV (RISC-V Vector) Extension

• Vector load/store, vector-fused multiply-add (VFMA), and matrix computation acceleration
• Variable-length vector operations (VL, VLEN) for workload-optimized SIMD execution
• Vector mask operations, segment control, and data type flexibility for DSP and ML workloads

Custom DSP and Domain-Specific Instruction Design

• Creating domain-specific accelerators via custom extensions and CBAR-based operand interfaces
• Modifying compiler frontends for custom instruction generation and code emission
• Hardware-software partitioning strategies for integrating accelerators into production SoCs

AI Acceleration and Edge Machine Learning on RISC-V

NPU Design and Integration for RISC-V Processors

• Neural Processing Unit architecture: systolic arrays, tensor cores, and weight compression for on-chip AI acceleration
• Model quantization techniques (INT8, INT4, FP8) for edge deployment on RISC-V
• Framework compatibility: TensorFlow Lite Micro, ONNX Runtime, and PyTorch Edge on RISC-V targets

Heterogeneous Computing for AI Workloads

• Co-design of RISC-V host CPUs with AI accelerator NPUs for real-time inference pipelines
• Optimizing memory subsystems: managing HBM/DDR bandwidth for ML model weights and activations
• Thermal and power budgeting for edge AI inference systems

Hardware Security and Confidential Computing on RISC-V

Physical Memory Protection and Trusted Execution

• Physical Memory Protection (PMP) and Page Table walker security mechanisms
• Secure Enclave/TEE architectures for RISC-V: OP-TEE integration and SEV-class trusted execution environments
• Boot chain security: establishing roots of trust, secure boot, and measured launch attestation

Cryptographic Acceleration

• RISC-V cryptographic extensions (Zk, Zkr, K extensions): accelerating SHA, AES, RSA, RSA-PSS, and ECC
• Integrating post-quantum cryptography (PQC) for next-generation RISC-V processors
• Mitigating side-channel attacks: employing constant-time programming, masking, and hardware random number generators

Advanced Custom Architecture and ISA Extension Design

Domain-Specific Architecture and Custom Instruction Extensions

• ISA extension design methodology: encoding, encoding tables, ABI impact analysis, and the RISC-V International specification submission process
• Designing custom register files with CBAR (Custom Base Address Registers) for operand dispatch
• Instruction pipelining, hazard detection, and pipeline modifications for custom extensions

Verification and Signoff of Custom Architecture Modifications

• Testbench design for custom extensions: directed versus constraint-random stimulus generation
• Regression testing frameworks and coverage-driven verification for architectural changes
• Interoperability testing: ensuring custom instructions function within established ABI constraints

Safety-Critical and Automotive RISC-V Applications

Functional Safety and Automotive Standards Compliance

• ISO 26262 functional safety compliance for RISC-V automotive processors
• ASIL-Q classification and safety manual development for RISC-V silicon IP
• Deterministic interrupt handling, lockstep core pairs, and memory protection for safety-critical RISC-V systems

Industrial Real-Time and Edge Computing Applications

• IEC 61508 SIL compliance and deterministic scheduling on RISC-V multicore platforms
• Developing Industrial IoT gateways with RISC-V: connectivity, edge analytics, and OTA firmware update systems

Capstone Project: End-to-End RISC-V System Development

Full Lifecycle Project

• Architecture specification: designing ISA extensions and core configuration for a defined use case
• RTL implementation in SystemVerilog with UVM testbenches and formal verification coverage
• FPGA prototyping, boot firmware development, and bare-metal driver stack integration
• Customizing Linux BSP and toolchains for the custom RISC-V core
• Deploying AI workloads: NPU integration, model quantization, and performance benchmarking
• Security validation: enforcing PMP, secure boot, and benchmarking cryptographic acceleration
• Documenting technical architecture, analyzing IP strategy, and presenting to cross-functional teams